Scalable strained fet device and method of fabricating the same

ABSTRACT

A CMOS FET device having an enhanced performance is described by taking advantage of known dual-stress-liner effects and by making use of compressive nitride in an appropriate geometric configuration to induce compressive stress in the n-FET channel, and a tensile stress in the p-FET. The stress enhancement is designed to be insensitive to PC pitch, and to increase by reducing the height of the polysilicon stack, such that scalability contributes to the stated performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners to be greater than 3 GPa, compared to less than 1.5 GPa for tensile liners.

FIELD OF THE INVENTION

The invention is related to semiconductor devices, and moreparticularly, to field effect transistors (FETs) showing an improvedperformance by incorporating scalable stressed channels.

BACKGROUND OF THE INVENTION

The ability to scale CMOS devices to smaller dimensions has allowedintegrated circuits to experience continuous performance enhancements.Moreover, in spite of economic considerations, constraints on devicedesigns and materials are hampering further improvements in scaling thedevices. Since constraints in scaling are imposing fast approachinglimits beyond which technical and economic constraints make additionalscaling unappealing, new techniques have been developed to continuouslyincrease the device performance.

One alternative which has gained popularity is to impose certainmechanical stresses within a semiconductor device substrate which can beadvantageously used to modulate the device performance. For example, insilicon, hole mobility is enhanced when the silicon film is undercompressive stress, while the electron mobility is enhanced when thesilicon film is under tensile stress. Therefore, compressive and/ortensile stresses can be advantageously created in the channel regions ofa p-FET and/or an n-FET in order to enhance the performance of suchdevices. However, the same stress component whether compressive ortensile, discriminatively affects the performance of the p-FET and then-FET devices. Alternatively, compressive stress in the silicon, whileit enhances the performance of the p-FET, it adversely affects theperformance of the n-FET, while a tensile stress enhances theperformance of the n-FET while adversely impacting the performance ofthe p-FET. Therefore, p-FET and n-FET require different types ofstresses for performance enhancement, which imposes a challenge whenconcurrently fabricating high performance p-FET and n-FET devices, dueto the difficulty in simultaneously applying compressive stress to thep-FET and tensile stress to the n-FET.

One approach for creating desired compressive and tensile stresses inthe channel regions of p-FET and n-FET devices is to overlay the p-FETand the n-FET devices with separate compressive and tensile stresseddielectric films so that the tensile and compressive stresses can berespectively applied to the n-FET and p-FET devices.

Another problem of significance is the trend towards devices havingsmaller and smaller dimensions. Researchers have investigated the impactof technology scaling in reducing the effectiveness of virtually allknown stress enhancement techniques. Channel stress from stressed linersis reduced with a tighter PC pitch, shorter polysilicon stacks andembedded SiGe (and embedded carbon), wherein the effectiveness isreduced with smaller RX-past-PC dimensions, for example. Hence, whenmigrating from one technology node to the next, one must find ways toovercome the degradation associated with scaling and find additionaloptions to improve the technology performance further. Traditionally,this has been achieved by brute force, i.e., by way of higher stressliners, higher germanium content in eSiGe, and the like, or bysignificantly modifying the device materials/structure, such as embeddedSiC.

Present day stress devices are currently manufactured with a stressinducing liner that is advantageously formed atop the gate region, theexposed surface of the substrate adjacent to the gate region andsilicide contacts. An example of such stress devices is found, e.g., inU.S. Pat. No. 7,002,209 to Xiangdon Chen et al., of common assignee. Thepatent describes methods of forming a liner such that it contacts thesidewalls of the gate conductor. When thin sidewall spacers are used,the stress inducing liner is positioned on the thin sidewall spacer suchthat the thin sidewall spacer separates the stress inducing liner fromthe gate region. The stress inducing liner is deposited under conditionsthat create a compressive or a tensile stress. The method described inthe aforementioned patent, however, is limited to the use of a singlestress liner.

Another problem arising by the ever shrinking ground rules governinghigh performance technologies is caused by the loss of stress whenreducing the pitch of the gate electrode conductor. This phenomenon hasbeen described in the current literature, and more particularly in thepaper “1-D and 2-D effects in uniaxially-strained dual etch stop layerstressor integrations” by Paul Grudowski et al., published in the Digestof Technical Papers of the 2006 Symposium on VLSI Technology. Thereinare described a detailed electrical and simulation characterization of2-D boundary effects and 1-D poly pitch response of highly stressed dualetch stop layer integrations, and how these effects impact achievabletransistor performance gains and improved circuit designs. A contactetch stop layer used as a stressor has demonstrated significantperformance improvements, particularly when employed in a dualintegration. Still, the problem caused by continuously scaling down thedevices remains.

A further problem imposed by traditional scaling methods is caused bythe loss of stress when reducing the height of the gate electrodeconductor. This phenomenon has also been described in the currentliterature, and more particularly in a paper “MOSFET Current DriveOptimization Using Silicon Nitride Capping Layer for 65-nm TechnologyNode” by S. Pidin et al., published in the Digest of Technical Papers ofthe 2004 Symposium on VLSI Technology. Therein is described a simulationcharacterization of device channel stress response to gate electrodeheight for highly stressed etch stop layers. Thus, a tradeoff isestablished between the traditional scaling benefits of gate heightreduction, namely parasitic capacitance reduction due to a reduced gatesidewall area, and the stress imparted to the channel from a stressedliner.

In order to better appreciate the advantages, aspects and benefits ofthe present invention, prior art stressed complementary FET devices willnow be described in order to distinguish the device structure of thepresent invention when it is compared to conventional prior art devices.

Referring to FIG. 1 a, there is shown a pair of complementary FETdevices (i.e., n-FET and p-FET) illustrating a first stress liner atopthe transistor already patterned to induce the desired mobility gain.The first stress liner can be either tensile or compressive andthickness ranges from 40 nm-100 nm, with 50 nm being more typical. Thestress liner in FIG. 1 a is patterned using standard lithography andetching techniques where the stress liner is left on top of the devicesthat result in a mechanical strain favorable for increasing the mobilityof the carriers. Tensile stress liners impart a stress that increasesthe electron mobility, while compressive stress liners impart a stressthat increases the hole mobility. The stress liner is preferably anydielectric commonly used in semiconductor processing (SiN, SiO₂, SiCOH,HfO₂, SiCN, ZrO₂), although SiN is preferably used.

Referring to FIG. 1 b, the same pair of complementary FET devices aredepicted having a second stress liner already patterned. The secondstress liner should provide an opposing stress from that provided by thefirst stress liner and be removed from transistors that are covered bythe first stress liner. For example, if the first stress liner istensile, then the second stress liner should be compressive. The secondstress liner should preferably have a thickness ranging from 40 nm-100nm, with 50 nm being more typical. The second stress liner can be any ofthe standard dielectrics used in semiconductor processing (SiN, SiO₂,SiCOH, HfO₂, ZrO₂, SiCN), although SiN is more commonly used.

Still referring to FIG. 1 b, a thin oxide layer is deposited afterpatterning the first liner but before depositing the second liner inorder to achieve etch selectivity if the second stress liner is made ofa similar material as the first stress liner.

Next, referring to FIG. 2, another dielectric layer is deposited atopthe silicon wafer. The dielectric is typically a low temperature SiO₂deposition with thickness ranging from 150 nm-250 nm, with 210 nm beingmore typical.

Referring to FIG. 3, the same semiconductor structure is illustratedafter applying Chemical Mechanical Polish (CMP), resulting in the oxidebeing removed by this standard polishing step commonly used insemiconductor processing. The oxide is preferably removed until the topof the gate conductor electrodes are exposed, leaving no oxide. Thefinal surface needs to be flat with no surface topography to have thesurface directly above the target FET totally planarized.

The devices shown thus far suffer from a distinct degradation when thepitch between the complementary devices shrinks as the technologymigrates from one node to the next. During the pitch reduction, thelength of the stress nitride-silicon film interface is reduced, which ineffect, reduces the stress coupling from the liner to the silicon filmand MOSFET channel. In addition, the resulting stresses induced devicesshown thus far remain susceptible to degradation from gate heightreduction. This is because the stress in the channel is created by edgeforces induced at the stressed-liner/sidewall spacer/silicon filmintersection, the strength of which depend upon the poly height, as wellas stressed-liner thickness, poly pitch, and the like.

Accordingly, there is a need in industry for a process of forming dualstress liners in which enhanced n-FET stress from a compressive cap canbe achieved by reducing the polysilicon height without degradationduring PC pitch scaling.

OBJECTS AND SUMMARY OF INVENTION

Accordingly, it is an object of the present invention to provideenhanced FET devices displaying an improved performance by incorporatinga scalable stressed channel.

It is another object of the invention to improve the performance byproviding a dual-stress liner atop the gates of complementary FETdevices.

It is a further object to induce the n-FET stress from a compressive capwhich does not degrade with PC pitch scaling, and where enhancement fromthe compressive cap increases with gate height reduction.

It is still a further object to provide a compressive liner havingsignificantly higher stress than corresponding tensile counterparts.

It is a yet another object to make the inventive structure compatiblewith replacement gates while ensuring a low implementation cost.

In accordance of one aspect of the invention, the performance of a CMOSFET device improves significantly by taking advantage of knowndual-stress-liner effects, making use of compressive nitride in anappropriate geometric configuration to induce tensile stress in then-FET channel, and similarly employ a tensile nitride for compression inthe p-FET.

Of particular importance to this approach resides in its scalability.The stress enhancement is designed to be insensitive to PC pitch, adistinct advantage, and to increase by reducing the height of the gatestack. In addition, since the n-FET can leverage the higher stressvalues obtainable by compressive liners (i.e., >3 GPa, compared to <1.5GPa for tensile), considerable benefits with this approach areanticipated.

The present invention provides a semiconductor device that includes: atleast one n-channel field effect transistor (n-FET) and at least onep-channel field effect transistor (p-FET) that are spaced apart fromeach other on a substrate; and a first dielectric stressor layeroverlaying the gate of at least one n-FET and a second dielectricstressor layer overlaying the gate of at least one p-FET, wherein thefirst dielectric stressor layer is compressively stressed and the seconddielectric stressor layer is tensilely stressed.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptionof the invention taken in conjunction with the accompanying figures, inwhich:

FIG. 1 a is a schematic diagram illustrating prior art complementary FETdevices on a substrate wherein a first liner has been deposited inselected areas (up to middle-of-line (MOL) dielectric deposition);

FIG. 1 b is a schematic diagram illustrating the prior art complementarypair of FET devices in which a second liner has been deposited inselected areas (up to MOL dielectric deposition);

FIG. 2 is schematic diagram illustrating the two prior art complementaryFET devices of FIG. 1 b wherein a blanket oxide layer has been depositedatop the two devices;

FIG. 3 illustrates a schematic diagram in which the nitride layer on topof the polysilicon has been removed, preferably, by chemical mechanicalpolishing, in order to planarize the surface above the target FET; and

FIG. 4 illustrates improved devices wherein a compressive nitride caphas been deposited on top of the n-FET gate, and a compressive nitridecap or tensile nitride cap or a combination of a compressive layer thatincludes implant relaxation has been deposited on top of the p-FET gate,in accordance with a preferred embodiment of the present invention,wherein edge forces are induced at the two ends of the cap.

FIG. 5 illustrates the improved devices shown in FIG. 4, wherein thep-FET device is capped by a compressive nitride cap, in accordance withanother embodiment of the present invention.

FIG. 6 illustrates the improved devices shown in FIG. 4, wherein thestress cap technique is provided to the n-FET, leaving the p-FET devicefully uncapped, according to still another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous specific details are set forth,such as particular structures, components, materials, and dimensions, inorder to provide a thorough understanding of the present invention.However, it will be readily appreciated by one of ordinary skill in theart that the invention may be practiced without these specific details.In other instances, well-known structures or processing steps have notbeen described in detail in order to avoid obscuring the invention.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” another element, it can bedirectly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” another element, there are no intervening elements present. It willalso be understood that when an element is referred to being “connected”or “coupled” to another element, it is directly connected or coupled tothe other element or intervening elements may be present. In contrast,when an element is referred to as being “directly connected” or“directly coupled” to another element, there are no intervening elementspresent.

FIG. 4 shows a cross-sectional view of a CMOS device according to oneembodiment of the present invention.

The present invention provides an improved CMOS device that includes atleast one n-FET and at least one p-FET with a dielectric stressor,preferably a nitride layer, directly connected to the gate of each ofthe FET devices, hereinafter referred to as a “cap”. The dielectricstressor caps provide the desired stresses on the n-FET and the p-FETdevices.

More specifically, the CMOS device comprises an n-FET that is locatedover an n-FET active region 2 and a p-FET that is positioned over ap-FET active region 4. The n-FET active region 2 and p-FET active region4 are located in the same semiconductor substrate (not shown), separatedfrom each other by isolation region 11. The n-FET active region 2contains n-type source and drain doping regions (not shown) with sourceand drain silicide contacts 21 and 23. Similarly, the p-FET activeregion 4 contains n-type source and drain doping regions (not shown)with source and drain silicide contacts 41 and 43.

Separate gate structures, one of which is formed by: (1) a first gateconductor 24, (2) a gate metal silicide 25, and (3) and at least onespacer 27, and the other that includes: (1) a second gate conductor 44,(2) a second gate metal silicide 45, and (3) at least one spacer 47,which are formed over n-FET active region 2 and p-FET active region 4,respectively. Gate dielectrics 22 and 42 respectively isolate the n-FETactive region 2 and the p-FET active region 4 from the first and secondgate conductors 24 and 44.

The respective gates of the n-FET and p-FET are capped by stress layers,preferably by a compressively stressed nitride cap on top of the n-FET,and either by a compressively nitride cap or a tensilely nitride cap ora compressively stressed nitride cap that includes implant relaxation.

The dielectric stressor cap layers 50 and 60 preferably includes anysuitable dielectric material whose stress profiles can be modulated oradjusted. Preferably, but not necessarily, the continuous dielectricstressor layer 50 includes SiN.

The above-described stressor layers 50 and 60 is advantageously formedby a selective UV-treatment process, which has been found by theinventors of the present invention to be particularly effective inconverting compressive stress of a dielectric film into tensile stress.

Exemplary processing steps that can be used for forming the dielectricstressor cap 50 and 60 in the CMOS device structure illustrated by FIG.4 will now be described in greater detail. Note that in the drawing,which is not drawn to scale, like and/or corresponding elements arereferred to by like reference numerals. It is further noted that in thedrawings only one n-FET and one p-FET are shown. Although illustrationis made to such an embodiment, the present invention is not limited tothe formation of any specific number of n-FETs and/or p-FET devices, andcan easily include an array formation of such devices.

Still referring to FIG. 4, the semiconductor structure after depositingand patterning a stress liner layer (layer C in the drawing) is shownwhere the pattered layer is centered over the gate electrode. The edgesof stress liner C in FIG. 4 impart a mechanical stress on the channelthat can increase the mobility of the carriers.

The stress liner can be any dielectric used in semiconductor processing(SiN, SiO₂, SiCOH, HfO₂, ZrO₂, SiCN), although SiN is preferred. Thethickness of the stress liner ranges from 10 nm to 800 nm, but 40 nm ispreferred. The stress liner create either compressive or tensile stress;however, compressive stress is preferred since higher magnitudes ofstress can be achieved for compressive SiN stress liners compared totensile stress liners. Typical compressive SiN stress liners preferablyhave a stress value of 3 GPa or greater, while tensile SiN stress linershave a stress value of 1.5 GPa. The larger compressive stress liner hasbeen found to impart more stress, translating to a higher mobility gain.

The compressively stressed dielectric layer, as mentioned previously, ismade, e.g., of SiN, which can be readily formed by plasma-enhancedchemical vapor deposition (PECVD) process or a high-density plasma (HDP)process that is carried out at a temperature ranging from about 300° C.to about 450° C., a pressure ranging from about 0.5 torr to about 6torr, and a plasma power level ranging from about 100 W to about 1500 W,using processing gases that include trimethylsilane, NH₃, and N₂.

Still referring to FIG. 4, a compressive stress liner (liner C) resultsin providing tensile mechanical stress in the transistor channel;therefore, it is best to pattern the stress liner C over the n-FETtransistor to produce the desired gains in performance.

Referring back to previously described FIG. 1 b, a tensile stress lineron the n-FET was illustrated and a compressive stress liner on thep-FET. The tensile (compressive) nitride on the source drain regions ofthe n-FET (p-FET) induces a tensile (compressive) stress in the channelregion, which in turn improves the electron (hole) mobility within thechannel. The magnitude of the stress induced in the silicon depends on(among other factors) the lateral extent of the nitride away from thesilicon channel. During scaling, due to the ground rule shrink, adjacentgates become closer to each other. This results in the lateral extent ofthe nitride becoming smaller and so the stress induced in the channelalso reduces.

Still referring to FIG. 1 b, while the nitride film on top of the sourceand drain regions induced tensile stress in the channel, the tensilenitride on top of the gate, in contrast, induced a compressive stress inthe channel reducing the stress caused by the nitride film at thebottom. Further, as the height of the gate is reduced, the top nitridecomes closer to the channel and the compressive stress induced by thisnitride film increases. Thus, reducing the gate height also reduces thestress induced by the whole tensile nitride film (for a given stress inthe nitride film).

Now referring to FIG. 4, the tensile nitride is removed only from thetop of the n-FET and is replaced with a compressive nitride layer. Thecompressive liner is then etched, creating an edge force at each of thecompressive liner sidewalls, as indicated in the drawing. Thecompressive nitride on top of the gate induces a tensile stress in thesilicon channel (opposite of what the tensile nitride film on top of thegate earlier induced). This adds to the tensile stress being induced bythe tensile nitride over the source-drain regions, increasing the stressin the channel. Bringing the compressive nitride on top of the gatecloser to the channel, (i.e., by reducing the gate height) increases thetensile stress induced in the channel. Finally, it is observed that thelateral extent (or the length) of the compressive nitride does not needto scale as the pitch (distance between two adjacent devices) isreduced. The present inventive method circumvents the problem related tothe reduction of the improvement when the pitch is scaled downward.Finally, the use of a compressive nitride film is of particular benefitto n-FET devices having compressive nitride films of approximately 3.5GPa. This has been demonstrated experimentally. In contrast, the higheststress that has been obtained for tensile films is of the order of 1.5GPa.

Although the above invention has been described for n-FET devices, theconclusions are equally applicable to p-FETs, but the stress of thevarious stress films is reversed. Thus, the stress film over the sourceand drain would optimally be compressive in nature, while the stressfilm over the gate is tensile in nature.

For optimal performance, one would simultaneously form tensile stressedliner caps on p-FETs and compressive stressed liner caps on n-FETs.However, performance advantage can be obtained with at lower cost orcomplexity by selectively capping either the n-FETs or the p-FETs, andperforming an implant relaxation into the stressed cap covering thesub-optimally configured device (i.e., p-FET with compressive cap, orn-FET with tensile cap). Alternatively, one can employ siliconsubstrates in which one FET type is relatively insensitive to stress,and employ a single stressed liner cap to improve the performance of theother. For example, (001) silicon wafers, with gates oriented along<100> axes result in p-FETs which are rather insensitive to stress. Inthis case, a compressive cap on the n-FET and p-FET would be preferredand most economical implementation of this structure, as illustrated inFIG. 5.

One advantage of patterning a compressive liner C, illustrated in FIG.4, is the increase in mechanical stress that arises from the verticaledge force of the patterned film. The stress from the edge force adds tothe mechanical stress in the channel already present from stress linerB. In addition, current state of the art compressive liners achieve muchhigher levels of stress compared to tensile liners (3.5 GPa forcompressive versus 1.5 GPa for tensile). Using the compressive liner onthe n-FET transistor is not possible in the conventional dual stressliner approach illustrated in FIGS. 1 a-1 b (prior art) as it wouldresult in an undesirable compressive stress in the channel of the n-FET(since the compressive stress degrades n-FET mobility but enhances thehole mobility). However, creating a planarized flat surface using CMP(FIG. 3) with a patterned compressive liner on the flat surface (FIG. 4)gives rise to an edge force that imparts tensile stress in the channelof the MOSFET, and which has shown to be very beneficial for n-FETdevice improvement. Therefore this structure enables the use of highermagnitude compressive stress films on n-FET transistors to help maximizeperformance.

An additional advantage of the structure illustrated in FIG. 4 is thatit reduces the sensitivity to spacing between gate electrodes. One ofthe problems with using the known prior art of dual stress liners asillustrated in FIGS. 1 a-1 b is the reduction of stress as the spacingbetween the gate electrodes diminishes.

Practitioners of the art will recognize that under certain constraints,the drive current can decrease as the spacing between the gateelectrodes shrinks. This degradation arises because there is less volumeof the stress liner material for applying stress in the channel of theMOSFET. Since the length (or volume) of the liner C depends only weaklyon the distance between the 2 gates—i.e., the length is pitchinsensitive—then the stress it applies is independent of the technologypitch.

Finally, the present structure shows that the stress increases as thethickness of the gate electrode is reduced. Reducing the thickness inadvanced CMOS technology is desirable and can only enhance the stressgained from the patterned stress liner C.

Referring to FIG. 6, another embodiment of the invention shows the p-FETdevice without any cap atop the gate of the device. This is valid aslong as the other (i.e., complementary) device is provided with anappropriate stressed cap on its corresponding gate. The benefit obtainedis comparable to the compressive+implant solution, but it clearly savesthe cost of the relaxation implant and added lithography.

While the present invention has been particularly described, inconjunction with a specific preferred embodiment, it is evident thatmany alternatives, modifications and variations will be apparent tothose skilled in the art in light of the present description. It istherefore contemplated that the appended claims will embrace any suchalternatives, modifications and variations as falling within the truescope and spirit of the present invention.

1. A semiconductor device comprising: at least one n-channel fieldeffect transistor (n-FET) and at least one p-channel field effecttransistor (p-FET) that are spaced apart from each other on a substrate;and a first dielectric stressor layer overlaying a gate of said at leastone n-FET and a second dielectric stressor layer overlaying a gate ofsaid at least one p-FET, wherein said first dielectric stressor layer iscompressively stressed and said second dielectric stressor layer istensilely stressed.
 2. The semiconductor device of claim 1, wherein saidsecond dielectric stressor layer is a nitrate cap overlaying only one ofsaid at least one p-FET gate and said at least one n-FET gate.
 3. Thesemiconductor device of claim 2, wherein said second dielectric stressorlayer is a compressive nitride cap.
 4. The semiconductor device of claim2, wherein said second dielectric stressor is compressively stressed incombination with implant relaxation.
 5. The semiconductor device ofclaim 2, wherein no cap overlays said second p-FET gate.
 6. Thesemiconductor device of claim 1, wherein said first and seconddielectric stressor have a thickness ranging from 40 nm to 100 nm. 7.The semiconductor device of claim 1, wherein said first dielectricstressor layer is selected from the group consisting of SiN, SiO₂,SiCOH, HfO₂, and ZrO₂.
 8. The semiconductor device of claim 1, wherein atop exposed surface is planarized prior to depositing the first andsecond dielectric stressor layers to a level essentially equal to theheight of said n-FET and p-FET.
 9. An array of semiconductor devicescomprising: a plurality of n-channel field effect transistors (n-FET)and p-channel field effect transistors (p-FET), each pair of said n-FETand p-FETs being spaced apart from each other on a substrate; and afirst dielectric stressor layer respectively overlaying a gate of eachof said n-FETs and a second dielectric stressor layer overlaying a gateof each of said p-FETs, wherein said first dielectric stressor layer iscompressively stressed and said second dielectric stressor layer istensilely stressed
 10. A method for forming a semiconductor devicecomprising: forming at least one n-channel field effect transistor(n-FET) and at least one p-channel field effect transistor (p-FET) thatare spaced apart from each other; and forming a first dielectricstressor layer overlaying a gate of said at least one n-FET and a seconddielectric stressor layer overlaying a gate of said at least one p-FET,wherein said first dielectric stressor layer is compressively stressedand said second dielectric stressor layer is tensilely stressed.
 11. Themethod of claim 10, wherein said second dielectric stressor layer is anitrate cap overlaying only one of said at least one p-FET gate and saidat least one n-FET gate.
 12. The method of claim 10, wherein said seconddielectric stressor layer overlaying said at least one p-FET is atensile nitride cap.
 13. The method of claim 10, wherein said seconddielectric stressor layer overlaying said at least one p-FET is acompressive nitride cap.
 14. The method of claim 10, wherein said seconddielectric stressor layer overlaying said at least one p-FET is acompressive nitride cap in combination with implant relaxation.
 15. Themethod of claim 10, wherein no cap overlays said second said at leastone p-FET gate.
 16. The method of claim 10, wherein said wherein saidfirst and second dielectric stressor have a thickness ranging from 40 nmto 100 nm.
 17. The method of claim 10, wherein said first dielectricstressor layer is selected from the group consisting of SiN, SiO₂,SiCOH, HfO₂, and ZrO₂.